1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device (EEPROM), specifically to a NAND-type flash memory.
2. Description of the Related Art
A NAND-type flash memory is known as one of electrically rewritable and highly-integrated non-volatile semiconductor memory devices. In the NAND-type flash memory, multiple memory cells are connected in series in such a manner that adjacent two cells share a source/drain diffusion layer, thereby constituting a NAND cell unit (i.e., NAND string). The respective ends of the NAND string are coupled to a bit line and a source line via select gate transistors. By use of such a NAND-sting structure, a large capacity of memory device may be achieved with a small unit cell area in comparison with a NOR-type flash memory.
A memory cell in the NAND-type flash memory has a charge storage layer (e.g., floating gate) formed on a semiconductor substrate with a tunnel insulating film interposed therebetween, and a control gate stacked on the floating gate with an inter-gate insulating film interposed therebetween, and stores data in a non-volatile manner in accordance with a charge storage state in the floating gate. Explaining in detail, binary data storage may be defined as follows: a high threshold state obtained by injecting electrons into the floating gate is defined as, for example, data “0” while a low threshold state obtained by discharging the electrons in the floating gate as data “1”. Recently, such a multi-level data storage scheme (for example, a four-level data storage scheme) is made to be usable that the write threshold distribution is divided into multiple levels.
Data program or write of the NAND-type flash memory is performed by a page. One page is defined as a set of memory cells arranged along a selected word line or the half. Explaining in detail, data write is performed by applying program or write voltage Vpgm to a selected word line, thereby injecting electrons into the floating gate from the cell channel with FN tunneling current. In this data write mode, channel potentials of the respective NAND cells are controlled via the corresponding bit lines in accordance with write data “0” and “1”.
In detail, in case of “0” writing, the corresponding bit line is set at Vss, and this bit line potential will be transferred to the selected cell's channel via a select gate transistor. In this case, when a selected word line is applied with write voltage Vpgm, large electric field is applied between the floating gate and the cell channel in the selected cell, so that electrons are injected into the floating gate. By contrast, in case of “1” writing (i.e., write-inhibiting), the corresponding bit line is set at Vdd. As a result, the selected cell's channel is charged up to Vdd-Vth (Vth is threshold voltage of the select gate transistor) via the select gate transistor to be set in a floating state. In this case, when the selected word line is applied with write voltage Vpgm, the selected cell's channel is boosted in potential by capacitive coupling from the selected word line, so that electron injection into the floating gate will be inhibited.
Prior to data writing, data erasing is performed for resetting the cells in a block to be in a negative threshold state. Explaining in detail, data erase is performed by: applying 0V to all word lines in the block and applying erase voltage Vera to the cell p-type well, thereby discharging electrons in the floating gates of all cells in the block to the cell p-type well.
Erase-verify for verifying the erase state is performed in such a way as to detect that the threshold voltage of all cells in the NAND string have been set to be negative. The erase-verify is performed in principle by judging whether cell current flows or not in the cell channel from the corresponding bit line under the condition that all word lines are set at a certain voltage equal to the ground potential or higher than it (for example, 0V). For example, refer to JPA-2004-030897.
However, under the condition that negative voltage can not be used, the above-described method has such a limit that it is detected only whether the cell threshold is set to be under 0V or not. To detect a negative threshold voltage of an erased cell, it will be used such a method that cell current is carried in the NAND string from the source line CELSRC to the bit line BL as reverse to the normal read mode.
That is, under the condition that all word lines in the NAND string are set at 0V, cell current is carried from the cell source line CELSRC to the bit line BL. If the threshold voltage of all cells is set at about −Vth, the bit line will be charged up to Vth. Therefore, detect this bit line charged level, and the negative threshold voltage may be detected. For example, refer to JPA-2007-305204.
On the other hand, there is another method for verifying erased cell's threshold voltage with such a scheme that cell current is carried from the bit line to the cell source line as similar to the normal read operation. This is for substantially verifying the cell's negative threshold voltage under the condition that word lines are set at 0V; the source line and the cell p-type well are applied with positive voltage V0; and the bit lines and select gate lines are applied with the positive voltage V0 in addition to the normal driving voltages. For example, refer to JPA-2008-103003.
Although, some erase-verify methods have been explained above, as a problem of erase-verifying, there is a possibility that a cell underlying a word line adjacent to a select gate line is erroneously judged as erased due to a noise from the select gate line in spite of that it is not sufficiently erased. That is, when a select gate line is applied with a select voltage for coupling a NAND string to a bit line, a word line adjacent to the select gate line (i.e., adjacent word line), which is to be kept at 0V, is temporally boosted in potential due to capacitive coupling. As a result, the cell underlying the adjacent word line is turned on in spite of that it is not erased, and it leads to erroneous judgment that the erase-verify is passed.
This problem becomes larger in accordance with that the integration and capacity of the cell array are made progress. Further, in case it is in need of setting precisely narrow cell's threshold distributions for a multi-level data storage scheme, there is a probability that it becomes difficult to set the threshold distribution.